1. Field of the Invention
The present invention relates generally to an electrically rewritable semiconductor memory, such as an EEPROM. More specifically, the invention relates to a semiconductor memory having a redundant circuit for replacing a defective memory cell.
2. Description of the Related Background Art
In typical large scale semiconductor memories, a redundant circuit system for relieving a device having a certain range of defective memory cells is adopted in order to improve producing yields. The redundant circuit systems include three types, i.e., a column redundant circuit for replacing a defective bit line with a spare bit line, a row redundant circuit for replacing a defective word line with a spare word line, and a combination thereof.
A memory of a redundant circuit system has a defective address storing circuit, such as a fuse circuit, for nonvolatilisably storing a defective address. Then, the coincidence of an input address with a defective address is detected to output an detection output. In response to the coincidence detection output, the memory cell of the defective address is replaced with a memory cell of a redundant circuit.
However, in conventional EEPROMs, the relief efficiency using the redundant circuit is not high Because it is not possible to cope with a plurality of defective columns or rows even if redundant circuits corresponding to one column or one row are arranged at the end portion of a memory cell array. In addition, even if redundant circuits corresponding to one column or one row are arranged at the end portion of the memory cell, there is a strong possibility that the redundant circuits themselves at the end portion of the cell array will be defective. This also lowers the relief efficiency.